About me
Current Location: Venice Beach, Los Angeles, California, USA
Dual-National (British/Irish) with both passports plus US green card (EB1A Visa).
20+ years programming experience in various languages (C/C++/Python/Typescript) and 10+ years ASIC hardware design (Cadence/Synopsys/Calibre) mainly digital, but some analog. Speciality skills include asynchronous logic design, subthreshold design and physical modelling.
I also have 5+ years experience working in AI research, principally focused on novel bitwise AI architectures.
I started web development by learning HTML using Dreamweaver, LAMP stacks, Flash and ActionScript in my teens and have remained up to date with the topic ever since.
jordan@jordanmorris.co.uk
Education - Newcastle University, UK
PhD - VLSI Design and Semiconductor Physics
iCase award (Sponsored PhD)
Served at Arm HQ, Cambridge UK
Applied Silicon Research Team
(Small 9-man research group with
3 of the original 12 founders)
Thesis
2018-2013MEng - Electrical and Electronic Engineering
summa cum laude
with first class honours
2013-2012BEng - Electrical and Electronic Engineering
2012-2009Projects
Publications
Pre-Sorted Tsetlin Machine (The Genetic K-Medoid Method)
J. Morris, A. Yakovlev, Pre-Print, ISTM (International Symposium on the Tsetlin Machine), 2024
An Event Driven Approach To Genotype Imputation On A RISC-V Cluster
J. Morris, A. Rafiev, G. Bragg, M. Vousden, D. B. Thomas, A. Yakovlev, A. D. Brown, IEEE Transactions on Computational Biology and Bioinformatics, 2023
Event-based High Throughput Computing: A Series of Case Studies on a Massively Parallel Softcore Machine
M. Vousden, J. Morris, G. M. Bragg, J. Beaumont, A. Rafiev, W. Luk, D. Thomas, A. D. Brown, IET Computers & Digital Techniques, 2022
A Subthreshold Layout Strategy for Faster and Lower Energy Complex Digital Circuits
J. Morris, P. Prabhat, J. Myers, A. Yakovlev, Journal of Low Power Electronics and Applications 12, no. 3: 43, 2022
An Alternate Feedback Mechanism for Tsetlin Machines on Parallel Architectures
J. Morris, A. Rafiev, F. Xia, R. Shafik, A. Yakovlev, O. C. Granmo, A. D. Brown, 2022 IEEE International Symposium on Tsetlin Machines, Grimstadt
Visualization of Machine Learning Dynamics in Tsetlin Machines
A. Rafiev, J. Morris, F. Xia, R. Shafik, A. Yakovlev, O. C. Granmo, A. D. Brown, 2022 IEEE International Symposium on Tsetlin Machines, Grimstadt
Practical Distributed Implementation of Very Large Scale Petri Net Simulations
A. Rafiev, J. Morris, F. Xia, A. Yakovlev, M. Naylor, S. Moore, D. B. Thomas, G. M. Bragg, M. Vousden, A. D. Brown, In: Koutny, M., Kordon, F., Moldt, D. (eds) Transactions on Petri Nets and Other Models of Concurrency XVI. Lecture Notes in Computer Science, vol 13220. Springer, Berlin, Heidelberg
Low-Latency Asynchronous Logic Design for Inference at the Edge
A. Wheeldon, A. Yakovlev, R. Shafik and J. Morris, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021, pp. 370-373
Self-timed, Minimum Latency Circuits for the Internet of Things
A. Wheeldon, J. Morris, D. Sokolov, A. Yakovlev, Integration 2019, 69, 138-146
Unconventional Layout Techniques for a High Performance, Low Variability Subthreshold Standard Cell Library
J. Morris, P. Prabhat, J. Myers and A. Yakovlev, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, 2017, pp. 19-24
Power-Proportional Adder Design for Internet of Things in a 65nm Process
A. Wheeldon, J. Morris, D. Sokolov and A. Yakovlev, 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Thessaloniki, 2017, pp. 1-6.
Software Skills
Recent Experience
- Typescript/Javascript
- C
- C++
- Python
- Bash
- CUDA
- MPI
Previous Experience
- .NET
- Visual Basic
- Java
Hardware Skills
Languages
- Verilog/SystemVerilog
- VHDL
Cadence Digital ASIC Flow
- Xcelium
- Genus
- Innovus
- Tempus
- Voltus
- Joules
- Quantus
- Pegasus
- Conformal
- JasperGold
Cadence Analog ASIC Flow
- Virtuoso
- ADEXL
- Spectre
Synopsys Digital ASIC Flow
- VCS
- Design Compiler
- IC Compiler
- PrimeTime
Physical ASIC Design
- HSpice
- SiliconSmart
- Liberate
FPGA Design
- Xilinx Vivado
- Intel Quartus
Niche Skills
- Asynchronous Logic Design
- Subthreshold Physics
Web Development Skills
- MERN Stack
- Next.js
- SQL
- Tailwind
- Sass
External Development Courses
2023 - Hardware-Efficient Machine Learning | 2 days | IMEC Academy, Leuven
2019 - Comprehensive Digital IC Implementation and Sign-Off (using Cadence Tools) | 5 days | Europractice MSC STFC Rutherford Appleton Laboratory
2018 - Advanced Low Power Digital IC Implementation (using Cadence Tools) | 3 days | Europractice MSC STFC Rutherford Appleton Laboratory
2017 - Real Time Software Design with UML | 5 days | Feabhas Onsite
2017 - Advanced C Programming | 5 days | Feabhas Onsite
2015 - Introduction to FPGA Design using Xilinx Vivado Tools | 2 days | Europractice MSC STFC Rutherford Appleton Laboratory
2015 - Introduction to FPGA Design using Altera Quartus II | 2 days | Europractice MSC STFC Rutherford Appleton Laboratory
2015 - Verilog and System Verilog for Design | 4 days | Europractice MSC STFC Rutherford Appleton Laboratory
2015 - Comprehensive Digital IC Implementation and Sign-Off (using Synopsys Tools) | 5 days | Europractice MSC STFC Rutherford Appleton Laboratory
2014 - Introduction to Analogue and Mixed Signal IC Design | 5 days | Europractice MSC STFC Rutherford Appleton Laboratory
2014 - Introduction to Technology CAD using Synopsys Sentaurus TCAD Tools | 3 days | Europractice MSC STFC Rutherford Appleton Laboratory
2014 - Mixed Signal IC Design and Implementation | 4 days | Europractice MSC STFC Rutherford Appleton Laboratory
2013 - Analog IC Design, Simulation, Layout and Verification | 5 days | Europractice MSC STFC Rutherford Appleton Laboratory
